VLSI Designing of Low Power Radix4 Booths Multiplier

Abstract

The operation of multiplication is present in several parts of a digital system or digital computer. It is extensively used in signal processing, graphics and scientific computation. With advancement in technology, various techniques have been proposed to design multipliers, with higher speed, lower power consumption and lesser area. Thus high speeds, low power compact VLSI implementations can be accomplished. These three parameters i.e. power, area and speed are always main traded off to accomplish. Multiplication involves two basic operations: the generation of partial products and their accumulation. Partial products can be reduced by using the Radix_4 modified Booth algorithm. The parallel multipliers like radix 4 modified booth multiplier do the computations using lesser adders and lesser iterative steps. The design is proposed for implementation of Booth multiplier using VHDL. This compares the power consumption and delay of radix 2 and modified Booth multipliers. The modified Booth multiplier with ripple carry adder will have power reduction than the conventional radix 2 Booth Multiplier.